The present invention relates to an active matrix display apparatus of the dot sequentially driven type, and more particularly to a display apparatus of the type mentioned which adopts a technique of suppressing crosstalk between pixels and so forth to assure a high picture quality.
An active matrix display apparatus uses a 1H inversion driving method wherein, when it performs dot sequential driving, a video signal to be written into pixels is inverted for each one horizontal scanning period (1H). In the 1H inversion driving, if charging/discharging current upon writing of a video signal into a signal line provided for each column of pixels disposed in rows and columns in high, then a defect called “vertical stripe” appears on the display screen. To suppress the charging/discharging current upon writing of a video signal as low as possible, a precharge drive method wherein a precharge signal is written prior to writing of a video signal is adopted conventionally.
A vertical stripe of a medium gray level is most likely to appear among such vertical stripes. Accordingly, a gray level with which a vertical stripe is most likely to appear is normally set as a level for a precharge signal. However, if the potential for the precharge signal is set to a gray level, then when a window pattern or the like is displayed, crosstalk in a vertical direction (such crosstalk may be hereinafter referred to as vertical crosstalk) is sometimes caused by the fact that the light leak amount between the source and the drain of a pixel transistor locally differs, and deteriorates the picture quality.
To prevent occurrence of such vertical crosstalk, the precharge signal should be set to a black level. Where the precharge signal is set in this manner, the leak current between the source and the drain of a pixel transistor becomes uniform over the entire screen. However, if the precharge signal is set to a black level, then a vertical stripe described above becomes likely to appear conversely. In other words, the “vertical crosstalk” and the “vertical stripe” have a relationship of tradeoff to each other.
Taking the foregoing into consideration, a “dot sequential 2-step precharge method” wherein a black level and a gray level are precharged at two steps has been proposed and is disclosed, for example, in Japanese Patent Laid-Open No. 2000-267067. An example of an active matrix display apparatus which adopts the dot sequential 2-step precharge method is shown in FIG. 9. FIG. 9 shows a general configuration of the display apparatus. Referring to FIG. 9, the display apparatus 0 shown includes a pixel array section 9, a pair of vertical drive circuits 4, a horizontal drive circuit 6 and a precharge drive circuit 8. The pixel array section 9 includes gate lines 1 extending in the direction of a row, signal lines 2 extending in the direction of a column, and pixels 3 disposed in rows and columns at points at which the gate lines 1 and the signal lines 2 intersect with each other. The vertical drive circuits 4 are connected to the gate lines 1 and successively select the pixels 3 in the individual rows in a predetermined vertical scanning period. The horizontal drive circuit 6 is connected to the signal lines 2 and writes a video signal dot-sequentially into the pixels 3 of a selected row within a predetermined horizontal period. It is to be noted that, though not shown, the video signal is supplied through predetermine video signal lines. Also the precharge drive circuit 8 is connected to the signal lines 2 and writes precharge signals of a black level and a gray level into the pixels in accordance with a dot sequential 2-step precharge method.
FIG. 10 shows a particular example of a configuration of the precharge drive circuit shown in FIG. 9. Referring to FIG. 10, in the configuration example shown, the precharge drive circuit 8 includes a shift register formed from flip-flops S/R connected at multiple stages. The shift register operates in response to a precharge clock PCK supplied thereto from the outside and successively transfers a precharge start pulse PST supplied thereto from the outside similarly to output shift pulses A, B, C, . . . . Further, precharge lines 7 for supplying precharge signals are disposed between the precharge drive circuit 8 and the pixel array section positioned on the upper side of the precharge drive circuit 8. The precharge signals are supplied from the outside through the precharge lines 7. In the arrangement shown in FIG. 10, four such precharge lines 7 are provided. The two upper side ones of the precharge lines 7 supply precharge signals PSIG-Gray1 and PSIG-Gray2 of a gray level, respectively. The two lower side ones of the precharge lines 7 supply precharge signals PSIG-Black1 and PSIG-Black2 of a black level, respectively. Further, a precharge switch set is provided between the precharge lines 7 and the signal lines 2 of the pixel array section side. In the arrangement shown in FIG. 10, a precharge switch PSWG is provided for each of the signal lines 2 corresponding to the upper side two precharge lines 7. Meanwhile, a precharge switch PSWB is provided for each of the signal lines 2 corresponding to the lower side two precharge lines 7. The first precharge switch PSWG is connected to the first precharge line 7, and the second precharge switch PSWG is connected to the second precharge line. In this manner, the precharge switches PSWG are connected alternately to the first and second precharge lines 7. Similarly, also the precharge switches PSWB are connected alternately to the third and fourth precharge lines 7. The precharge switches PSWG are driven to be opened or closed simultaneously for each set including two precharge switches PSWG. Also the precharge switches PSWB are driven to be opened or closed simultaneously for each set including two precharge switches PSWB. Generally, by driving a plurality of precharge switches to be opened or closed simultaneously as a unit, the frequency of the precharge clock PCK can be suppressed. However, the precharge switches may alternatively be driven successively one by one.
The shift pulse A outputted from the first stage of the shift register which forms the precharge drive circuit 8 is used to drive the precharge switches PSWG of the first set and the precharge switches PSWB of the second set to be opened and closed. The shift pulse B outputted from the second stage of the shift register is used to drive the precharge switches PSWG of the second set and the precharge switches PSWB of the third set to be opened and closed. The shift pulse C outputted from the third stage of the shift register is used to drive the precharge switches PSWG of the third set and the precharge switches PSWB of the fourth set to be opened and closed. While the precharge drive circuit 8 successively drives the precharge switches to be opened or closed in this manner, if attention is paid to one of the signal lines 2, normally a precharge switch PSWB is driven to be opened or closed first, and then a precharge switch PSWG is driven to be opened or closed. In other words, the precharge drive circuit 8 is configured such that the precharge signals PSIG-Black1 and PSIG-Black2 of the black level are sampled on the signal lines first, and then the precharge signals PSIG-Gray1 and PSIG-Gray2 of the gray level are sampled on the same signal lines.
It is to be noted that each of the pixels 3 included in the pixel array section is formed, in the arrangement shown in FIG. 10, from a liquid crystal cell LC and a pixel transistor TFT. The gate electrode of the pixel transistor TFT is connected to the corresponding gate line 1, and the source electrode is connected to the corresponding signal line 2 while the drain electrode is connected to the pixel electrode of the corresponding liquid crystal cell LC. The other electrode of the liquid crystal cell LC is grounded to a counter-potential VCOM through a common line.
FIG. 11 is a waveform diagram illustrating operation of the precharge circuit shown in FIG. 10. As described above, the shift register of the precharge drive circuit 8 operates in response to the precharge clock PCK to transfer the precharge start pulse PST to successively output shift pulses A, B, C, . . . . The precharge switches PSWG of the first set are opened in response to the shift pulse A, and the precharge signals of the gray level are held by the corresponding signal lines. Simultaneously, also the precharge switches PSWB of the second set are opened, and the precharge signals of the black level are held by the preceding signal lines. In this manner, dot sequence precharge driving is performed in accordance with the two-step method wherein the precharge signals of the black level are sampled first and then the precharge signals of the gray level are sampled. Naturally, the dot sequence precharge driving is performed in prior to successive writing of video signals into the pixels 3. By sampling the precharge signals of the black level first, “vertical crosstalk” is suppressed, and then by sampling the precharge signals of the gray level, a “vertical stripe” can be suppressed.
FIG. 12 illustrates the waveforms of the precharge signals PSIG-Black1 and PSIG-Gray1 supplied to the precharge lines 7. The precharge signal PSIG-Black1 exhibits an inversion after each 1H with respect to the counter-potential VCOM, and the level PSIG-Black therefor is set to the black. In the example shown in FIG. 12, the counter-potential VCOM is 7.5 V, and the level PSIG-Black is 7.5±5.0 V. It is to be noted that also the other precharge signal PSIG-Black2 of the black level has a same waveform as that of the precharge signal PSIG-Black1. On the other hand, also the precharge signal PSIG-Gray1 exhibits an inversion after each 1H with respect to the counter-potential VCOM, and the potential level PSIG-Gray therefor is set to a gray level (7.5±2.5 V) of a half tone. This similarly applies also to the other precharge signal PSIG-Gray2.
In a display apparatus of an ordinary resolution, a distance of approximately 20 μm can be assured between signal lines. In this instance, one precharge switch PSWG and one precharge switch PSWB can be disposed corresponding to each of the signal lines 2 as seen in FIG. 10. Accordingly, in the conventional precharge drive circuit shown in FIG. 10, the precharge switches PSWG and the precharge switches PSWB can be disposed in an overlapping relationship with each other in two stages.
On the other hand, in a display apparatus for the high definition television system, the distance between signal lines is reduced to approximately 10 μm. In this instance, an area sufficient to allocate switches to signal lines in a one-by-one corresponding relationship is not assured. Therefore, the precharge switches are disposed in an upwardly and downwardly displaced relationship as seen in FIG. 13. More particularly, of the precharge switches PSWG for writing a gray level, the odd-numbered ones are disposed in the upper stage while the even-numbered ones are disposed in the lower stage. According to the arrangement just described, an area corresponding to two signal lines can be allocated to one precharge switch PSWG. However, different from the arrangement of FIG. 10, the precharge switches PSWG must be arranged not in one stage but in two upper and lower stages. Similarly, also the precharge switches PSWB for writing the black level are divided into two upper and lower stages. Accordingly, in a panel of a high definition, where the conventional 2-step dot sequential precharge driving method is applied, the precharge switches must be arranged in four upper and lower stages. In this manner, as the pixel pitch decreases as a result of increase of the definition of a panel and reduction of the panel size, the precharge switches PSW cannot be laid out within a pitch of one pixel any more. Therefore, the precharge switches PSW must be laid out in two overlapping stages in a pitch of 2 pixels as seen in FIG. 13. However, where the precharge switches PSWB and PSWG are placed individually in two overlapping stages, the precharge switches PSW are placed totally in four stages, and there is a problem that the space becomes insufficient and the precharge switches PSW cannot be laid out.